1. Field of the Invention
This invention relates to delay cells and, more particularly, to a differential delay cell with differential control inputs for use in Voltage Controlled Oscillators (“VCO”) and delay lines. The differential delay cell can be implemented using CMOS or BiCMOS technologies.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase-locked loops (“PLL's”) and delay-locked loops (“DLL's”) are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. In some cases, for example, PLL's and DLL's may be used in the I/O interfaces of digital integrated circuits to hide clock distribution delays and to improve overall system timing. In general, a PLL or DLL may be used to generate one or more clocking signals that are in phase alignment with a reference clock. More specifically, a PLL is a closed-loop device that uses a voltage-controlled oscillator (VCO) to obtain accurate phase alignment between the generated clocking signals and the reference signal. A DLL device, on the other hand, generally differs from a PLL device in that it uses a delay line, instead of a VCO, to obtain accurate phase alignment between the clocking and reference signals.
Unfortunately, the rising demand for high-speed electronics has created an increasingly noisy environment in which PLL's and DLL's must function. This noise, typically in the form of power supply and substrate noise, may cause the output clocks (i.e., the clocking signals) of a PLL or DLL to jitter from their ideal timing. Jitter often leads to decreased stability around the operating frequency (otherwise referred to as the “center frequency”). With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter PLL's and DLL's has become very challenging.
Achieving low jitter in PLL and DLL designs can be difficult due to a number of design tradeoffs. Consider, for example, a typical PLL based on a voltage-controlled oscillator. The amount of jitter produced as a result of power supply and substrate noise is directly related to how quickly the PLL can correct the output frequency. To reduce jitter, the loop bandwidth (i.e., the range of possible frequencies within the PLL) should be set as high as possible. Unfortunately, the loop bandwidth is generally affected by many process technology factors, and thus, is often constrained well below the lowest operating frequency for stability. In some cases, these constraints can cause the PLL to have a narrow operating frequency range (since the loop bandwidth is directly dependent on the VCO gain) and poor noise performance.
VCO's are often fabricated using GaAs or bipolar technology to obtain high operation frequencies and better noise performance. Due to the increasing demand for lower cost and higher integration, however, VCO's have recently been fabricated using CMOS technology to obtain operating frequencies of several Gigahertz. Still, phase-noise reduction remains a challenge for typical CMOS voltage controlled oscillators.
CMOS LC-tank oscillators with an on-chip spiral inductor have been studied to improve phase-noise performance. Although CMOS LC-tank oscillators show some possibilities for better noise performance, CMOS LC-tank oscillators must overcome several barriers before becoming a reliable VCO. In particular, the implementation of a high-quality inductor in a standard CMOS process is often limited by parasitic effects and usually requires extra non-standard processing steps. Moreover, the integrated LC-tank oscillator generally demonstrates a narrow tuning range, thereby making the performance of the PLL sensitive to process variations.
A ring oscillator, on the other hand, can be smoothly integrated into a standard CMOS process without requiring extra processing steps (since it does not require passive resonant elements). In addition, a wide operating range may be easily obtained when the ring oscillator is employed as a VCO. However, the ring oscillator is not without limitations and usually demonstrates poorer phase-noise performance than the LC-tank oscillator. In some cases, differential delay cells have been employed within ring oscillators in an attempt to reduce phase-noise. These delay cells, however, cannot achieve maximum noise rejection since they are not truly differential.